my understanding is that effective processing speed is still limited by how fast the buses can transport data to and fro .. i have no idea just how the designers are taking this into account. here's a random example- It deals with professional-grade systems but the points are generally valid I think -

Computational SoC cores, which encompass microprocessor, microcontroller, and DSP engines, do a wonderful job of taking in and crunching the data, and then preparing computed results for use elsewhere on the chip. Computational speed has become less of a problem than moving data in and out of the processing core. Transferring data to and from the core to other chip logic is part of the job of the chip's bus.

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On-chip buses hence need three attributes—speed, flexibility, and bandwidth—to meet design-specific requirements. Flexibility for multi-core designs is often addressed outside of the core architecture, often with wrappers that go around silicon IP and act as a go-between from the IP to the bus. Speed may be limited by a silicon-process' interconnect parasitics and the physical implementation of the chip. This leaves bandwidth as the bus property with the most potential for meeting tomorrow's SoC-based system requirements.