What SDAI-Tech1 describes is the famous "von Neuman bootleneck", viz. the speed of a computer is limited by the bandwidth or data transfer rate of the computer's memory. Years ago, clever electrical engineers were saying that Moore's Law would be limited by the computer's memory bus. Supposably 1 GHz was an impassable wall based upon microwave resonant length arguments. Fortunately Intel's and AMD's engineers were even more clever by providing a memory cache residing on the chip's die that could run as fast as the CPU. The memory's circuits were much smaller than the resonant lengths of 3 GHz thus enabling the higher speed. However the cache has to be refilled or the CPU goes into a wait state. Again the clever engineers came up with an optimal cache size along with fast and cleverly organized RAM. However even with clever caching the RAM is now going about as fast as it can. Couple that with CPU heat flux and it becomes clear that Moore's Law has hit the wall. The only way now for more cycles/sec is parallel processors, e.g. dual core chips. However very few people know how to write efficient code for parallel machines, i.e. multi-threading. The machine that I am writing this post on is a dual CPU SMP box. However the only programs that make full use of its architecture are the Linux kernel and the DVD playing codes like Xine and Mplayer. I still like running an SMP box because it's operation is very smooth. Also I can run an aeroshell sizing code in background while the kids are watching Sponge Bob.

Gary